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IEEE Standard for Ethernet Amendment 6: Media Access Control (MAC) Service Interface and Management Parameters to Support Improved Precision Time Protocol (PTP) Timestamping Accuracy (Published), 2023
- Front Cover
- Title page
- Important Notices and Disclaimers Concerning IEEE Standards Documents
- Participants
- Introduction
- Contents
- 1. Introduction [Go to Page]
- 1.5 Abbreviations
- 30. Management [Go to Page]
- 30.2 Managed objects [Go to Page]
- 30.2.5 Capabilities
- 30.13 Management for oTimeSync entity [Go to Page]
- 30.13.1 TimeSync entity managed object class [Go to Page]
- 30.13.1.1 aTimeSyncCapabilityNsTX
- 30.13.1.2 aTimeSyncCapabilityNsRX
- 30.13.1.3 aTimeSyncDelayNsTXmax
- 30.13.1.4 aTimeSyncDelayNsTXmin
- 30.13.1.5 aTimeSyncDelayNsRXmax
- 30.13.1.6 aTimeSyncDelayNsRXmin
- 30.13.1.7 aTimeSyncCapabilitySubNsTX
- 30.13.1.8 aTimeSyncCapabilitySubNsRX
- 30.13.1.9 aTimeSyncDelaySubNsTXmax
- 30.13.1.10 aTimeSyncDelaySubNsTXmin
- 30.13.1.11 aTimeSyncDelaySubNsRXmax
- 30.13.1.12 aTimeSyncDelaySubNsRXmin
- 30.13.1.13 aTimeSyncCapabilityDdmp
- 30.13.1.14 aTimeSyncSelectionDdmp
- 30.13.1.15 aTimeSyncCapabilityMultiplePcsLane
- 30.13.1.16 aTimeSyncCapabilityDynamicPathDataDelay
- 45. Management Data Input/Output (MDIO) Interface [Go to Page]
- 45.2 MDIO Interface registers [Go to Page]
- 45.2.1 PMA/PMD registers [Go to Page]
- 45.2.1.175 TimeSync PMA/PMD capability (Register 1.1800)
- 45.2.1.176 TimeSync PMA/PMD transmit path data delay (Registers 1.1801, 1.1802, 1.1803, 1.1804, 1.1809, and 1.1810)
- 45.2.1.177 TimeSync PMA/PMD receive path data delay (Registers 1.1805, 1.1806, 1.1807, 1.1808, 1.1811, and 1.1812)
- 45.2.2 WIS registers [Go to Page]
- 45.2.2.20 TimeSync WIS capability (Register 2.1800)
- 45.2.2.21 TimeSync WIS transmit path data delay (Registers 2.1801, 2.1802, 2.1803, 2.1804, 2.1809, and 2.1810)
- 45.2.2.22 TimeSync WIS receive path data delay (Registers 2.1805, 2.1806, 2.1807, 2.1808, 2.1811, and 2.1812)
- 45.2.3 PCS registers [Go to Page]
- 45.2.3.67 TimeSync PCS capability (Register 3.1800) [Go to Page]
- 45.2.3.67.1 Data delay measurement point ability (3.1800.13:12)
- 45.2.3.67.2 Multilane ability (3.1800.11)
- 45.2.3.67.3 PCS dynamic path data delay ability (3.1800.10)
- 45.2.3.67.4 TimeSync transmit path data delay ability, in sub-ns (3.1800.3)
- 45.2.3.67.5 TimeSync receive path data delay ability, in sub-ns (3.1800.2)
- 45.2.3.67.6 TimeSync transmit path data delay ability, in ns (3.1800.1)
- 45.2.3.67.7 TimeSync receive path data delay ability, in ns (3.1800.0)
- 45.2.3.68 TimeSync PCS transmit path data delay (Registers 3.1801, 3.1802, 3.1803, 3.1804, 3.1809, and 3.1810)
- 45.2.3.69 TimeSync PCS receive path data delay (Registers 3.1805, 3.1806, 3.1807, 3.1808, 3.1811, and 3.1812)
- 45.2.3.69a TimeSync PCS configuration (Register 3.1813) [Go to Page]
- 45.2.3.69a.1 Data delay measurement point (3.1813.13)
- 45.2.4 PHY XS registers [Go to Page]
- 45.2.4.28 TimeSync PHY XS capability (Register 4.1800)
- 45.2.4.29 TimeSync PHY XS transmit path data delay (Registers 4.1801, 4.1802, 4.1803, 4.1804, 4.1809, and 4.1810)
- 45.2.4.30 TimeSync PHY XS receive path data delay (Registers 4.1805, 4.1806, 4.1807, 4.1808, 4.1811, and 4.1812)
- 45.2.5 DTE XS registers [Go to Page]
- 45.2.5.28 TimeSync DTE XS capability (Register 5.1800) [Go to Page]
- 45.2.5.28.1 Data delay measurement point ability (5.1800.13:12)
- 45.2.5.28.2 TimeSync transmit path data delay ability, in sub-ns (5.1800.3)
- 45.2.5.28.3 TimeSync receive path data delay ability, in sub-ns (5.1800.2)
- 45.2.5.28.4 TimeSync transmit path data delay ability, in ns (5.1800.1)
- 45.2.5.28.5 TimeSync receive path data delay ability, in ns (5.1800.0)
- 45.2.5.29 TimeSync DTE XS transmit path data delay (Registers 5.1801, 5.1802, 5.1803, 5.1804, 5.1809, and 5.1810)
- 45.2.5.30 TimeSync DTE XS receive path data delay (Registers 5.1805, 5.1806, 5.1807, 5.1808, 5.1811, and 5.1812)
- 45.2.5.31 TimeSync DTE XS configuration (Register 5.1813) [Go to Page]
- 45.2.5.31.1 Data delay measurement point (5.1813.13)
- 45.2.6 TC registers [Go to Page]
- 45.2.6.14 TimeSync TC capability (Register 6.1800)
- 45.2.6.15 TimeSync TC transmit path data delay (Registers 6.1801, 6.1802, 6.1803, 6.1804, 6.1809, and 6.1810)
- 45.2.6.16 TimeSync TC receive path data delay (Registers 6.1805, 6.1806, 6.1807, 6.1808, 6.1811, and 6.1812)
- 90. Ethernet support for time synchronization protocols [Go to Page]
- 90.2 Overview
- 90.3 Relationship with other IEEE standards
- 90.4 Time Synchronization Service Interface (TSSI) [Go to Page]
- 90.4.1 Introduction [Go to Page]
- 90.4.1.1 Interlayer service interfaces
- 90.4.1.2 Responsibilities of TimeSync Client
- 90.4.2 TSSI
- 90.4.3 Detailed service specification [Go to Page]
- 90.4.3.1 TS_TX.indication primitive [Go to Page]
- 90.4.3.1.1 Semantics
- 90.4.3.1.2 Condition for generation
- 90.4.3.1.3 Effect of receipt
- 90.4.3.2 TS_RX.indication primitive [Go to Page]
- 90.4.3.2.1 Semantics
- 90.4.3.2.2 Condition for generation
- 90.4.3.2.3 Effect of receipt
- 90.5 generic Reconciliation Sublayer (gRS) [Go to Page]
- 90.5.1 TS_SFD_Detect_TX TS_DDMP_Detect_TX function
- 90.5.2 TS_SFD_Detect_RX TS_DDMP_Detect_RX function
- 90.5.3 Dynamic transmit path data delay
- 90.5.4 Dynamic receive path data delay
- 90.6 Overview of management features
- 90.7 Path dData delay measurement [Go to Page]
- 90.7.1 FEC and PCS lane distribution functions
- 90.7.2 Alignment marker, codeword marker, and idle insertion/removal functions
- 90.7.3 Lane skew
- 90.8 Protocol implementation conformance statement (PICS) proforma for Clause 90, Ethernet support for time synchronization protocols [Go to Page]
- 90.8.3 TSSI indication
- 90.8.4 DDMP selectionData delay reporting
- Annex A (informative) Bibliography
- Annex 90A (informative) Timestamping accuracy considerations [Go to Page]
- 90A.1 Sub-nanosecond timestamping introduction
- 90A.2 Sub-nanosecond timestamping background
- 90A.3 Considerations for use of different data delay measurement points
- 90A.4 Considerations for multiple PCS lane functions
- 90A.5 Considerations for alignment marker/codeword marker and idle functions [Go to Page]
- 90A.5.1 Example use of TX_NUM_BIT_CHANGE and PDPDD
- 90A.5.2 Example use of RX_NUM_BIT_CHANGE and PDPDD
- 90A.5.3 Considerations for implementations without TX_NUM_BIT_CHANGE and RX_NUM_BIT_CHANGE
- 90A.6 Considerations for transmit skew
- 90A.7 General method for dealing with repeating delay variation patterns
- Back Cover [Go to Page]
